The RISC-V project is almost over, just some tests have to be completed. This week I was doing the controller module that generates control signals after decoding the instructions. I then made the cult_div module.
It was easy to make these modules as I had the reference code in Verilog for the V-scale processor.
While writing the test for must_div module I faced some problems as I was not getting the expected output. I couldn’t figure out why that happened. So, now my project partner is debugging the code.
I m now currently writing tests for controller module and trying to figure out how exactly the controller works by giving some inputs and checking the output.
Hopefully we will complete this project within a week.