The HDMI receiver core is almost over, I have been reading the xilinx application notes for the HDMI receiver IP core. I will complete the HDMI receiver IP core soon and then start debugging it.
The receiver core is more complicated than the transmitter core. In the receiver there are modules for word boundary detection, channel deskew, etc, which were not present and are not needed in the transmitter.
I learnt how to account for xilinx primitives in the code using MyHDL. xilinx primitives are modules which have a dedicated space for them in the FPGA, so that we need not waste the logic gate space for them. We have to use user defined code feature for this case and we can implement the logic using MyHDL (so that simulations can be done) and use the xilinx primitive module only when the code is converted to verilog.